1. Field of the Invention
The present invention relates to a semiconductor memory having redundant cells. More particularly, the invention relates to a semiconductor memory capable of being verified for the use or the nonuse of redundant cells therein.
2. Description of the Related Art
Semiconductor memories generally include redundant bits illustratively composed of redundant memory cell rows and columns. These redundant bits are provided to compensate for faulty bits in the semiconductor memories while maintaining high levels of yield of their fabrication.
Such semiconductor memories having redundant bits are generally tested for the use or the nonuse of redundant bits therein.
FIG. 30 is a circuit diagram of a redundant bit usage test circuit for use with a conventional semiconductor memory. The circuit of FIG. 30 is what is disclosed in Japanese Patent Publication No. Hei 2-41117.
Referring to FIG. 30, an input terminal 401 receives as a test signal a potential higher than a supply voltage VCC. A supply potential line 404 is fed with the supply potential VCC. A plurality of MOSFET diodes 402 and a fuse 403 are connected in a serial and interposing manner between the input terminal 401 and the supply potential line 404. The fuse 403 blows if any redundant bit is used.
The circuit of FIG. 30 works as follows: when the semiconductor memory is tested for the use or the nonuse of any redundant bit therein, the input terminal 401 receives a potential higher than the supply potential VCC. Then a check is made to see if a current flows through the fuse 403.
When a potential higher than the supply potential VCC is added to the input terminal 401, the multiple MOSFET diodes 402 are turned on each.
If no redundant bit is used, the fuse 403 remains intact and allows a current to flow therethrough. If any redundant bit has been used, the fuse 403 has blown and no current flows through it.
The test checks to see if any current flows through the fuse 403. The result of the test indicates whether or not any redundant bit has been used.
What follows is a description of another conventional semiconductor memory verifiable for the use or the nonuse of redundant bits therein.
FIG. 31 is a block diagram of a conventional semiconductor memory capable of being verified for the use or the nonuse of redundant bits therein. The semiconductor memory of FIG. 31 is what is disclosed in "A Fast 8K.times.8 Mixed CMOS Static RAM," IEEE Transactions on Electron Devices, Vol. ED-32, No. 9, September 1985.
Referring to FIG. 31, the semiconductor memory comprises a memory cell array 2, a redundant memory cell column 4, a row address buffer 11, a row decoder 12, a column address buffer 13, a column decoder 14, a multiplexer 15, a redundancy program circuit 17b, a redundant column decoder 18b, a redundancy multiplexer 19, a control circuit 66 and an input/output data buffer 600.
The memory cell array 2 includes a plurality of memory cells 20 arranged in matrix fashion. The redundant memory cell column 4 comprises a plurality of redundant memory cells 40 which constitute a column structure.
The row address buffer 11 receives a row address signal A0-An, amplifies the received signal, rectifies the amplified signal in waveform, and outputs the waveform-rectified signal. The row decoder 12 receives the output signal from the row address buffer 11, decodes the signal, and activates a memory cell row in the memory cell array 2 accordingly. This selects the appropriate memory cell row of the memory cell array 2.
The column address buffer 13 receives a column address signal B0-Bm, amplifies the received signal, rectifies the amplified signal in waveform, and outputs the waveform-rectified signal. The column decoder 14 receives the output signal from the column address buffer 13, decodes the signal, and supplies the decoded result to the multiplexer 15.
At the time of writing data, the multiplexer 15 selects a memory cell column in the memory cell array 2 in response to the output signal from the column decoder 14. The selected memory cell column is fed with write data from the input/output data buffer 600.
At the time of reading data, the multiplexer 15 selects a memory cell column in the memory cell array 2 in response to the output signal from the column decoder 14. The data is then read from the selected memory cell and given to the input/output data buffer 600.
In the redundancy program circuit 17b, the column address representing the column replaced by the redundant memory cell column 4 is programmed. In operation, the redundancy program circuit 17b receives a column address signal from the column address buffer 13. If the column address of the signal coincides with any column address programmed in the redundancy program circuit 17b, the circuit 17b generates a signal for inactivating the column decoder 14 and a signal for activating the redundant column decoder 18b.
The column decoder 14 is inactivated upon receipt of the signal from the redundancy program circuit 17b. The redundant column decoder 18b receives not only the signal from the redundancy program circuit 17b but also a test mode signal TE. The test mode signal is a signal that is activated in a test mode for testing the semiconductor memory for the use or the nonuse of redundant bits therein such as the redundant memory cell column 4.
The redundant column decoder 18b is activated in response to the signal from the redundancy program circuit 17b, and is inactivated upon receipt of the test mode signal TE. When activated, the redundant column decoder 18b supplies the redundancy multiplexer 19 with a signal for selecting a redundant memory cell column 4.
When data is to be written, the redundancy multiplexer 19 selects a redundant memory cell column 4 in response to the output signal from the redundant column decoder 18b. The selected redundant memory cell column 4 is fed with write data from the input/output data buffer 600. When data is to be read, the redundancy multiplexer 19 selects a redundant memory cell column 4 in response to the output signal from the redundant column decoder 18b. The data is read from the selected redundant memory cell column 4 and sent to the input/output data buffer 600.
The control circuit 66 receives a read/write control signal WE and outputs accordingly a control signal for controlling the input/output data buffer 600. The input/output data buffer 600 amplifies and otherwise handles a data input signal DI and a data output signal DO for a write and a read operation, respectively.
The input/output data buffer 600 receives the control signal from the control circuit 66. In response, the input/output data buffer 600 admits the data input signal DI or outputs the data output signal DO selectively.
More specifically, the input/output data buffer 600 sends the data input signal DI to the multiplexer 15 and redundancy multiplexer 19 for a read operation. The input/output data buffer 600 outputs the data write signal DO for a write operation to the outside.
Described below is how the semiconductor memory of FIG. 31 works in normal and in test mode.
(1) In normal mode
The memory cell row corresponding to a row address is selected as follows: the row address is first amplified and then waveform-rectified by the row address buffer 11. A row address signal from the row address buffer 11 is decoded by the row decoder 12. In turn, the row decoder 12 selects the appropriate memory cell row in the memory cell array 2.
The memory cell column corresponding to a column address is selected as follows: the column address B0-Bm is first amplified and then waveform-rectified by the column address buffer 13.
If the redundant memory cell column 4 has been used, the column decoder 14 and multiplexer 15 first select the corresponding memory cell column in the memory cell array 2. Then the redundant column decoder 18b and redundancy multiplexer 19 select the applicable redundant memory cell column 4.
It may happen that the column address of the column address signal from the column address buffer 13 fails to coincide with the column address programmed in the redundancy program circuit 17b. In that case, the output signal from the redundancy program circuit 17b activates the output signal of the column decoder 14 and inactivates the output signal of the redundant column decoder 18b.
In the case above, the column address signal from the column address buffer 13 is decoded by the column decoder 14. The output signal from the Column decoder 14 causes the multiplexer 15 to select the appropriate memory cell column in the memory cell array 2.
It may also happen that the column address of the column address signal from the column address buffer 13 coincides with the column address programmed in the redundancy program circuit 17b. In that case, the output signal from the redundancy program circuit 17b inactivates the output signal of the column decoder 14 and activates the output signal of the redundant column decoder 18b.
In the latter case, the output signal from the redundant column decoder 18b causes the redundancy multiplexer 19 to select the redundant memory cell column 4.
If the redundant memory cell column 4 has not been used, memory cell columns in the memory cell array 2 alone are selected by the column decoder 14 and multiplexer 15.
The memory cell thus designated by the selected row and column is subject to the data read or write operation.
When data is to be written, the read/write control signal WE is set for data write mode. On receiving the signal WE, the control signal 66 places the input/output data buffer 600 in data write mode. The data input signal DI is then written to the memory cell 20 via the reversed route of the read operation.
(2) In test mode
In test ode, the test mode signal TE is activated. This inactivates the redundant column decoder 18b, which in turn inactivates the redundancy multiplexer 19. As a result, the redundant memory column 4 is inhibited from being accessed for the write or read operation. Thus if the column address selected for a read operation represents the redundant memory cell column 4 replacing a memory cell column in the memory cell array 2, the read-out data is unpredictable.
In test mode, predetermined information is written beforehand to each of the addresses. The information is then retrieved from each address to verify whether or not the redundant memory cell column 4 has been used.
Where the predetermined information is retrieved from a column address, it may happen that column address represents the memory cell column replaced by the redundant memory cell column 4. In that case, the retrieved information is unpredictable. If the selected column address represents a memory cell column not replaced by the redundant memory cell column 4, the same predetermined information as that written beforehand is retrieved therefrom.
The use or the nonuse of the redundant memory cell column 4 is determined by whether or not the retrieved information coincides with the information previously written. A mismatch between the retrieved information and the already written information indicates that the memory cell column of the column address in question has been replaced by the redundant memory cell column 4.
Under such conventional schemes by which to check whether or not the redundant memory cell 4 is used, it is necessary to write and read the predetermined information to and from each address at least twice to make sure that the result of the check is correct. Writing and reading the information only once is not enough to ascertain that the retrieved information is not unpredictable information.
The conventional semiconductor memories exemplified by what is shown in FIGS. 30 and 31 have the following disadvantages:
The semiconductor memory having the test circuit of FIG. 30 requires generating a high voltage when the use or the nonuse of any redundant bits is verified. The voltage to be generated needs to be considerably high.
The reason for the high voltage is as follows: the threshold voltages of the MOSFET diodes 402 can be diverse depending on the fabrication process. To ensure that the test circuit functions normally requires that the disparate threshold voltages are to be exceeded by an appreciably high voltage.
Applying such a high voltage to the MOSFET diodes 402 produces a high voltage between their gates and the substrate. This can result in destruction of a gate insulating film.
Furthermore, the conventional redundant bit-usage test circuit exemplified by that of FIG. 30 needs dedicated signals for testing the high voltage and other aspects of operation. This means that the check on whether or not redundant bits are used cannot be performed efficiently.
The semiconductor memory of FIG. 31 requires repeating write and read operations repeatedly in test mode in order to make sure that the result of the check on the use or the nonuse of redundant bits is correct. It thus takes considerable time to ascertain the result of the check. This also means that the check on whether or not redundant bits are used cannot be performed efficiently.